Digital equipment is now commonplace in most types of electrical applications. However, in many of these applications, analog signals remain necessary and are often preferred. Thus, with the proliferation of digital equipment, digital to analog (D/A) signal convertors have also gained widespread use. Such convertors can take a variety of forms.
One well known and very straightforward type of D/A signal convertor utilizes a voltage scaling approach. With voltage scaling architecture, an N-bit digital input signal is converted to an analog output signal by a series string of 2.sup.N resistors connected between a reference voltage and ground sufficient to generate all of the required output voltages.
MOS transistors, preferable because they require virtually no input current and make excellent analog switches, are then used to switch the appropriate tap voltage to the output according to the applied digital input code. For a resistive load, voltage scaling D/A signal convertors also use an operational amplifier, configured as a voltage follower buffer, to provide a high impedance which prevents loading of the selected tap point. For a capacitive load, however, no such buffer is required. Moreover, voltage scaling D/A signal convertors are inherently monotonic.
Another well known type of D/A signal convertor utilizes a charge scaling approach. With charge scaling architecture, an N-bit digital input signal is converted to an analog output signal by a parallel array of 2.sup.N binary weighted capacitors connected between a reference voltage and ground sufficient to generate all of the required output voltages. Such capacitors, if properly laid out, match quite well in MOS technology, making charge scaling a feasible approach.
Thus, in charge scaling D/A signal convertors, MOS transistors are once again used to switch the appropriate capacitors to the reference voltage or ground according to the applied digital input code, thereby producing the correct analog output voltage. In contrast to voltage scaling D/A signal convertors, charge-scaling D/A signal convertors always require an operational amplifier, configured as a voltage follower buffer, at the analog signal output, regardless of the type of load involved.
Voltage scaling and charge scaling D/A signal convertors, however, both suffer from a similar problem. More specifically, the size of either the resistor string or capacitor array can become prohibitive as the number of bits in the digital input code increases. This is especially true for charge scaling D/A signal convertors considering that, for matching purposes, all capacitors must be integral sums of a unit capacitor.
For example, for a 10-bit digital input code, a voltage scaling D/A signal convertor would require a series string of 1024 unit resistors. Similarly, for the same 10-bit digital input code, a charge scaling D/A signal convertor would require a most significant bit (MSB) capacitor made from 512 unit capacitors connected in parallel.
One way to overcome this problem is to combine voltage scaling and charge scaling principles. With combined voltage and charge scaling architecture, an (N+K)-bit digital input signal is converted to a partial analog output signal by a series string of 2.sup.N resistors connected between a reference voltage and ground such that the available resistor segments are sufficient to generate all of the required output voltages for the N most significant bits of the digital input code.
Thereafter, switches attach an array of 2.sup.K binary weighted capacitors between the top and bottom of the previously selected resistor segment. The K least significant bits (LSB) of the digital input code are then applied to the capacitor array to produce a complete analog output signal. In this manner, an (N+K)-bit D/A signal conversion is performed.
Since the resistor string is inherently monotonic, the capacitor array must be ratio-accurate to only K-bits for the combined voltage and charge scaling D/A signal convertor to achieve monotonicity. More importantly, by combining voltage and charge scaling principles, the sizes of the resistor string and capacitor array are significantly reduced. More specifically, only a 2.sup.N resistor string and a 2.sup.K capacitor array are required, rather than a 2.sup.(N+K) resistor string or capacitor array individually.
Despite their advantages, combined voltage and charge scaling D/A signal convertors still suffer from significant problems. More specifically, the time required to charge a capacitive load at the output point limits the speed of a combined voltage and charge scaling D/A signal convertor. This becomes problematic as the speed requirement for the combined voltage and charge scaling D/A signal convertor increases.
Moreover, as with charge scaling D/A signal convertors, combined voltage and charge scaling D/A convertors must employ an operational amplifier, configured as a voltage follower buffer, at the analog signal output. Once again, as speed requirement increases, the size and power consumption requirements of the output buffer also increase. An example of a combined voltage and charge scaling D/A signal convertor that suffers from these problems can be found in U.S. Pat. No. 4,366,439 issued to Yamakido.
Thus, an improved D/A signal convertor would utilize the combined principles of voltage and charge scaling while simultaneously reducing the time necessary for charging a capacitive load. Such an improved D/A signal convertor would also reduce the size and/or power consumption requirements of the accompanying output buffer.